This invention relates to multiple processing systems and, more particularly, to a shared storage arrangement for such systems.
Systems of this nature have been described heretofore wherein multiple central processing units communicate through a shared storage unit. In addition to such communication, each of the central processing units (CPU's) has its own input/output devices. Many times a single bus structure is shared by all of the units on a time-shared basis which may lead to delays in processing time. In many cases, access to the shared or common memory is on a synchronous basis only. In addition, access of the common shared storage unit may be set up on a prioritized basis. Frequently, the CPU's are provided with their own independent storage, as well. Also, it has been known to provide interface units in a multiple processing system to resolve priority among the various processors requesting service.